Contact
RISC-V Architecture · Software Tools

Sergey
Yakushkin

I work at the intersection of computer architecture and systems software, focusing on RISC-V architecture and its software ecosystem. My work spans processor microarchitecture—including pipeline design, memory hierarchies, and custom ISA extensions—as well as hardware-software co-design, simulation, verification, compiler infrastructure, and the tools that make advanced hardware practical.

View Publications Areas of Focus
Computer Architecture · Software Tools
Open to collaborations on RISC-V
01 / About
Sergey Yakushkin
Intel · Synopsys · Huawei · Syntacore
7+
Publications
5+
Companies
5+
Awards
25+
Years Active

Designing Processors,
Building the Tools Around Them

I believe processor design and compiler development are inseparable disciplines. The most effective instruction set extensions are designed alongside the code generators that emit them and verified against realistic workloads from day one.

I have worked across academia and industry. My roles have included researcher at Intel and at the Institute for Communication Technologies and Embedded Systems at RWTH Aachen, architect and engineering manager at Synopsys, team leader at Huawei, and director of software engineering at Syntacore.

02 / Areas of Focus

Areas of Focus

RISC-V Microarchitecture

Research and development in out-of-order core design, branch prediction, cache hierarchies, prefetching, and SIMD and vector ISA extensions for domain-specific workloads.

OoO Branch Prediction Cache Vector ISA

Compiler & Software Ecosystem

LLVM backend development for RISC-V, spanning instruction selection, register allocation, profile-guided optimization, system software, and code-quality improvements for high-performance cores.

LLVM MetaWare PGO Code Generation

Hardware-Software Co-Design

Custom accelerator architectures, reconfigurable compute fabrics, and automated design frameworks that map workloads efficiently onto power-conscious silicon.

Accelerators HLS DSP Reconfigurable

Simulation & Verification

Functional and cycle-accurate simulation, trace-driven performance analysis, and robust verification pipelines for extensible processor cores.

Cycle-Accurate Trace Analysis Functional Sim Hybrid Sim
03 / Publications

Selected Work

2023
Compiler Optimization Challenges for High-performance RISC-V cores
S. Yakushkin, K. Vladimirov
RISC-V Summit China
2020
Callsite-aware profile-guided optimizations
P. Kosov, S. Yakushkin
LLVM Conference
2015
Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
S. Yakushkin, A. Bit, J. Campbell
Synopsys ARC White Papers
2012
A Next Generation Digital Signal Processor for European Space Missions
M. Odendahl, S. Yakoushkin, R. Leupers, E. Walter, M. Donati, L. Fanucci
IEEE-AESS ECSST
2012
Hybrid Simulation for Extensible Processor Cores
J. Jovic, S. Yakoushkin, L. Murillo, J. Eusse, R. Leupers, G. Ascheid
DATE
2010
MoonRidge: An Automated Design Framework for Workload-Optimized Power-Efficient Reconfigurable Accelerators
S. Yakoushkin, A. Redkin, A. Chun
HPCA, Workshop on SoC Architecture, Accelerators and Workloads
2007
Accelerator Exoskeleton
P. Wang, J. Collins, G. Chinya, H. Jiang, X. Tian, M. Girkar, L. Pearce, G-Y. Lueh, S. Yakoushkin, H. Wang
Intel Technology Journal, Vol 11, Issue 03
04 / Stack

Technologies

Architecture
RISC-V ISA Extensions Out-of-Order Caches x86
HDL
SystemVerilog Verilog Chisel nML LISA
Compilers
LLVM GCC Binutils TableGen MLIR
Simulation
gem5 Spike Verilator QEMU SystemC
Software
C++17 C Python Assembly HarmonyOS
05 / Contact

Let's Build
Something
Together

I am open to collaboration across the RISC-V ecosystem, hardware-software co-design, simulation infrastructure, and programming tools. Get in touch if you are working on an interesting challenge at the hardware-software boundary.

sergey@yakush.tech